1. Field of the Invention
The present invention relates to a method of producing a semiconductor device, more particularly relates to a method of producing a semiconductor device able to form a contact having a low resistivity and less variability in resistivity even if an aspect ratio is high.
2. Description of the Related Art
As a related art, a method of producing a contact hole will be explained with reference to FIGS. 1A to 1I.
First, as shown in FIG. 1A, a silicon substrate 1 is formed with an interlayer insulating film 2 comprised of for example a silicon oxide film. Alternatively, an interconnection layer comprised of metal can be used in place of the silicon substrate 1.
Next, as shown in FIG. 1B, a photolithography step is used to form a resist 3. Using the resist 3 as a mask, the interlayer insulating film 2 is etched to form an opening 4. After this, as shown in FIG. 1C, the resist 3 is removed. The silicon substrate 1 at the bottom of the opening 4 is therefore formed with a native oxide 5.
Next, as shown in FIG. 1D, reaction products deposited at the hatching part due to the etching for forming the opening 4 and the native oxide 5 are removed. Next, as shown in FIG. 1E, the opening 4 and the interlayer insulating film 2 are formed with a barrier metal layer 6 by for example chemical vapor deposition (CVD). After this, as shown in FIG. 1F, the barrier metal layer 6 is formed with a plug metal layer 7a comprised of for example tungsten (W) or another refractory metal by sputtering.
Next, as shown in FIG. 1G, the plug metal layer 7a and barrier metal layer 6 are etched back. Due to this, the opening 4 is formed with a plug 7 via the barrier metal layer 6. Next, as shown in FIG. 1H, the entire surface including the surface of the opening 4 is formed with an interconnection metal layer 8a comprised of for example aluminum (Al) or Al alloy. Here, a barrier metal layer comprised of Ti etc. can be formed on the interlayer insulating film 2 and plug 7 before the interconnection metal layer 8a is formed in the same way as the barrier metal 6 in the opening 4.
After this, using a not shown resist as a mask, the interconnection metal layer 8a is etched for forming interconnections 8 as shown in FIG. 1I. Due to the above process, a contact hole connecting the silicon substrate 1 or conductive layer and the upper interconnection layer 8 is formed.
In the above conventional method of forming a contact hole, while the native oxide 5 in the opening 4 is removed as a pre-treatment of forming the barrier metal layer 6, this process is often performed by wet-etching or argon (Ar) sputtering. A solution containing hydrofluoric acid (HF) is used for the wet-etching. Wet-etching has an advantage of a low cost of process.
On the other hand, Ar sputtering has become popularly employed as the aspect ratios of contact holes have increased. Since Ar sputtering can be performed using a conventional sputtering system, it is possible to form in-situ an interconnection or barrier metal layer by sputtering after removing a native oxide.
In recent years, the miniaturization of semiconductor devices has been accompanied by a miniaturization of contact holes and increase of aspect ratios. In the step of forming the barrier metal layer 6 shown in FIG. 1E, the aspect ratio becomes for example 7 or more. Even if the aspect ratio is a high one where a top diameter of the opening 4 is 0.4 xcexcm, a bottom diameter is 0.22 pm, and a height of the opening 4 is equal to a thickness of the interlayer insulating film 2 of 3 xcexcm, it is necessary to remove thoroughly the native oxide at the bottom of the opening 4 and the deposit on the sidewall of the opening 4.
However, according to the wet-etching or Ar sputtering described above, along with the increase of the aspect ratio, the following problems have becomes prominent. Due to this, the increase in resistivity in a contact hole having a high aspect ratio has becomes a serious problem.
When the wet-etching is performed in the step shown in FIG. 1D, as shown in FIG. 2A, a center part in a vertical direction is more easily etched in its sidewall (the interlayer insulating film 2) compared to the top and bottom of the opening 4. Along with the increase of the aspect ratio, the time required for wet-etching has become longer. Therefore, etching progresses particularly at the center part in the vertical direction of the opening 4 and therefore the opening 4 forms a barrel shape after the etching.
Due to this, it becomes impossible to fill the opening 4 with the plug metal layer 7a comprised of for example W with a good step coverage. Consequently, as shown in FIG. 2B, the plug 7 forming a part of the interconnections is formed with voids 9.
Also, as shown in FIG. 2A, the top diameter of the opening 4 becomes larger due to wet-etching. The dotted lines in FIG. 2A show an opening width of the resist 3 (see. FIG. 1B). When the top diameter of the opening 4 becomes larger, it becomes difficult to maintain a withstand voltage between contact holes next to each other. In the worst case, there is a short-circuit between the contact holes.
In the case of Ar sputtering, it suffers from the disadvantage that the resistivity rises due to damage on the contact part. In a contact hole of a high aspect ratio, when Ar sputtering is performed, as shown in FIG. 3A, the native oxide 5 is not removed uniformly at the bottom of the opening 4 and often remains near the sidewall of the opening 4. If the barrier metal 6 and plug 7 etc. are formed from this state as shown in FIG. 3B, a contact resistivity rises.
For the purpose of removing the native oxide 5 thoroughly and obtaining a predetermined resistivity, sputtering is performed by a certain amount on not only the native oxide 5 but also the surface of the underlying silicon substrate 1. If the sputtering is performed excessively, a contact 10 is damaged. For example, when the surface of the silicon substrate 1 is damaged and made amorphous, the reactivity of the barrier metal layer 6 formed above the silicon decreases and defects more easily appear at an interface.
Alternatively, when the sputtering is performed excessively, sputtered material may re-deposit at the contact part 10 and the resistivity may rise.
As described above, in the case of Ar sputtering, in both cases of inadequate sputtering and excessive sputtering, the resistivity of the contact part increases.
A pre-treatment method for forming interconnections able to overcome the above disadvantages without changing the shape of a contact hole and prevent an increase in resistivity at the contact part has been desired. As another pre-treatment method than wet-etching and Ar sputtering, plasma etching can be mentioned.
For example, Japanese Unexamined Patent Publication (Kokai) No. 4-186827 discloses a method of producing a semiconductor device characterized in that a gas containing fluorine is used as an etching gas and hydrogen gas is added for plasma etching before a contact hole is buried with metal. When reactive ion etching (RIE) is performed using a halide as an etching gas, the etching rate of silicon becomes higher than that of the silicon oxide film and a diffusion layer on the silicon substrate is etched largely.
Therefore, according to the method described in Japanese Unexamined Patent Publication (Kokai) No. 4-186827, hydrogen gas is added for lowering the etching rate of silicon. However, there is no description about the relationship between an inside pressure of a chamber and etching rate. An example shows etching is performed at 26 mTorr.
Also, Japanese Unexamined Patent Publication (Kokai) No. 8-45915 discloses a method of forming a contact hole reaching a surface of a metal layer by dry-etching an insulating layer on the metal layer. The method of forming a contact hole is characterized in that a gas containing a nitrogen atom is added to an etching gas and the amount of the gas containing a nitrogen atom is about 4.5% or more with respect to the etching gas other than the diluting gas. As a gas containing a nitrogen atom, N2, NH4, and NF3 are mentioned.
That invention was made for overcoming the disadvantage that it becomes impossible to remove metal deposited on the resist or sidewall of a contact hole by a subsequent washing step if the surface of the metal layer is sputtered with ions in plasma during dry-etching of the insulating layer. The etching step using an etching gas containing NF3 or another gas containing a nitrogen atom corresponds to the above described step shown in FIG. 1B.
Therefore, after forming the opening reaching the metal layer, the resist is removed and washing is performed in the same way as the step shown in FIG. 1C. An example shows that the photoresist and the deposit on the side wall of the contact hole are removed by washing with nitric acid and following washing with purified water.
As described above, the plasma etching described in Japanese Unexamined Patent Publication (Kokai) No. 8-45915 is applied to a step of forming the opening. It is expected that native oxide will be formed on the surface of the metal layer at the bottom of the opening after removing the resist and washing. Therefore, another treatment is required for removing the native oxide.
Japanese Unexamined Patent Publication (Kokai) No. 8-330537 describes a method of producing a semiconductor device comprising a step of forming in an interlayer insulating film formed on a semiconductor substrate a contact hole wherein the semiconductor substrate is exposed, a step of removing a native oxide at the bottom of the contact hole by plasma etching, and a step of forming an interconnection layer connecting to the semiconductor substrate via the contact hole. The method of production is characterized in that plasma etching is performed in a chemical dry etching (CDE) system wherein a plasma generating chamber and an etching reaction chamber are separated, NF3 is used as an etching gas, and the etching reaction chamber is made lower in pressure than the plasma generating chamber.
This invention was made for overcoming the disadvantage that the side wall of the contact hole is etched due to wet-etching or isotropic etching. When using anisotropic dry-etching, damage to the substrate becomes a problem in the same way as the Ar sputtering described above, while the change in shape of the contact hole due to isotropic dry-etching becomes problematic in the same way as wet-etching.
According to the etching method described in the Japanese Unexamined Patent Publication (Kokai) No. 8-330537, by separating the plasma generating chamber and etching reaction chamber, electrons having a low mass and high mobility are moved to a side wall of the plasma generating chamber. Due to this, a sheath is formed at the side wall of the plasma generating chamber. Due to the sheath, charged radicals are accelerated and strike the side wall of the plasma generating chamber. Non-charged neutral radicals move into the etching reaction chamber and participate in the etching. Since the inside pressure of the etching reaction chamber is lower than that of the plasma generating chamber, the mean free path of the neutral radicals entering the etching reaction chamber becomes longer. Due to this, the neutral radicals enter the contact hole in a predetermined direction.
According to this method of production, the etching gas is restricted to NF3 and other gases are not added for controlling the etching rate. The neutral radicals of low energy are selectively used for etching to prevent damage to the substrate. The inside pressure of the etching reaction chamber is controlled for guiding the entering neutral radicals. Also, nothing in particular is described regarding application to anything other than surface of the semiconductor substrate, for example, the surface of a metal layer. Further, since the plasma generating chamber and etching reaction chamber are separated, it is difficult to perform in-situ metal CVD for forming an interconnection layer after treatment for removing the native oxide.
Japanese Unexamined Patent Publication (Kokai) No. 4-72621 discloses a method of forming a semiconductor device characterized by etching native oxide in an atmosphere of a high temperature, preferably as much as 850xc2x0 C., and a high vacuum state where fluorine gas and hydrogen are introduced. According to the method, due to the addition of hydrogen gas into the fluorine compound gas, the concentration of fluorine radicals is adjusted and the etching rate of the silicon oxide is controlled to improve a selection ratio of silicon oxide and silicon.
As the fluorine compound gas, NF3, SF6, CF4, etc. are mentioned. When a gas containing carbon is used as the etching gas, it often becomes a problem that reaction products deposit on the sidewall of the contact hole.
Japanese Unexamined Patent Publication (Kokai) Nos.6-338478 and 10-321610 disclosed methods of producing a semiconductor device where native oxide is removed by adding NF3 gas or an NF3-containing gas to an activated gas obtained by changing a hydrogen-containing gas into plasma (hydrogen plasma downflow treatment). Japanese Unexamined Patent Publication (Kokai) No. 6-338478 describes that when NF3 gas is added into the activated gas of hydrogen-containing gas, the treatment time is shortened compared to the case where NF3 gas is not added.
Also, Japanese Unexamined Patent Publication (Kokai) No. 10-321610 describes that it is possible to increase the etching selection ratio of native oxide to another silicon oxide film formed by for example CVD or BPSG (borophosphosilicate glass) and remove the native oxide more selectively by performing the hydrogen plasma downflow treatment described in the above Japanese Unexamined Patent Publication (Kokai) No. 6-338478 at a lower predetermined temperature than room temperature by cooling the wafer.
According to the hydrogen plasma downflow treatment described in the Japanese Unexamined Patent Publication (Kokai) Nos. 6-338478 and 10-321610, NF3 is introduced to regions other than the plasma generating region. Therefore, although NF3 is activated by reacting with the hydrogen radicals, the NF3 is not activated by the electric field of the plasma generating region. When the native oxide is mainly removed by hydrogen radicals, the treatment time becomes longer.
As described above, it is already disclosed to perform pre-treatment for forming interconnections by plasma etching using fluorine compound gases. However, the optimum etching conditions etc. for reduding contact resistivity have not been investigated enough.
An object of the present invention is to provide a method of producing a semiconductor device able to prevent a change of shape of a contact hole and to form a contact having a low resistivity and low variability in resistivity.
According to the present invention, there is provided a method of producing a semiconductor device comprising the steps of forming a conductive layer in a substrate; forming an insulating layer on the conductive layer; forming an opening used as a contact hole in the insulating layer to penetrate the insulating layer and reach the conductive layer; and removing native oxide formed on a surface of the conductive layer at a bottom of the opening by plasma etching using an etching gas containing a fluorine compound gas at a predetermined concentration in a predetermined pressure wherein the concentration and pressure are determined within a range able to control an etching amount of the native oxide.
Preferably, the fluorine compound gas comprises nitrogen trifluoride (NF3) gas and an upper limit of the predetermined concentration of the NF3 gas is about 10%. Preferably, the etching gas comprises a helium (He) gas. Preferably, the predetermined pressure is not more than about 10 mTorr (≈1.33 Pa). Preferably, the etching amount is equivalent to about 0.5 to 10 nm of a thermal oxide film. Preferably, the method of producing a semiconductor device of the present invention further comprises the step of forming an interconnection at least in the opening without moving the substrate after the plasma etching.
Preferably, the plasma etching comprises inductively coupled plasma (ICP) etching, parallel plate etching, electron cyclotron resonance (ECR) etching, or high density plasma (HDP) etching.
Preferably, the conductive layer comprises a silicon (Si) layer, refractory metal silicide layer, refractory metal layer, refractory metal nitride layer, aluminum (Al) layer, or Al alloy layer.
More preferably, the refractory metal silicide layer comprises a cobalt silicide (CoSix) layer, titanium silicide (TiSix) layer, or tungsten silicide (Wsix) layer.
More preferably, the refractory metal layer comprises a titanium (Ti), tungsten (W) layer, or tantalum (Ta) layer.
More preferably, the refractory metal nitride layer comprises a titanium nitride (TiN) layer, tungsten nitride (WN) layer, or tantalum nitride (TaN) layer. More preferably, the Al alloy layer comprises an Alxe2x80x94Cu layer.
Due to this, it becomes possible to remove native oxide and reduce damage to the underlying layer exposed at the bottom of the opening even when a contact hole is formed at a high aspect ratio. Therefore, the contact resistivity can be decreased. Also, in the method of producing a semiconductor device of the present invention, it is possible to prevent formation of deposits containing carbon in the contact hole by performing plasma etching using NF3.
According to the method of producing a semiconductor device of the present invention, it is also possible to perform pre-treatment by plasma etching in the opening and forming an interconnection layer in the opening in-situ after forming the opening in an interlayer insulating layer.